`timescale 1ps/1ps
module map(
    input  [127:0] txt
,   output [7:0]  f00
,   output [7:0]  f01
,   output [7:0]  f02
,   output [7:0]  f03
,   output [7:0]  f10
,   output [7:0]  f11
,   output [7:0]  f12
,   output [7:0]  f13
,   output [7:0]  f20
,   output [7:0]  f21
,   output [7:0]  f22
,   output [7:0]  f23
,   output [7:0]  f30
,   output [7:0]  f31
,   output [7:0]  f32
,   output [7:0]  f33
);
/*
    (0,0)->txt[127:120]  (0,1)->txt[95:88]  (0,2)->txt[63:56]  (0,3)->txt[31:24] 
    (1,0)->txt[119:112]  (1,1)->txt[87:80]  (1,2)->txt[55:48]  (1,3)->txt[23:16] 
    (2,0)->txt[111:104]  (2,1)->txt[79:72]  (2,2)->txt[47:40]  (2,3)->txt[15: 8] 
    (3,0)->txt[103: 96]  (3,1)->txt[71:64]  (3,2)->txt[39:32]  (3,3)->txt[ 7: 0] 
*/

// wire[7:0]f00=txt[127:120];wire[7:0]f10=txt[95:88];wire[7:0]f20=txt[63:56];wire[7:0]f30=txt[31:24];  
// wire[7:0]f01=txt[119:112];wire[7:0]f11=txt[87:80];wire[7:0]f21=txt[55:48];wire[7:0]f31=txt[23:16];  
// wire[7:0]f02=txt[111:104];wire[7:0]f12=txt[79:72];wire[7:0]f22=txt[47:40];wire[7:0]f32=txt[15: 8];  
// wire[7:0]f03=txt[103: 96];wire[7:0]f13=txt[71:64];wire[7:0]f23=txt[39:32];wire[7:0]f33=txt[ 7: 0];

assign  f00=txt[127:120];assign  f01=txt[95:88];assign  f02=txt[63:56];assign  f03=txt[31:24];  
assign  f10=txt[119:112];assign  f11=txt[87:80];assign  f12=txt[55:48];assign  f13=txt[23:16];  
assign  f20=txt[111:104];assign  f21=txt[79:72];assign  f22=txt[47:40];assign  f23=txt[15: 8];  
assign  f30=txt[103: 96];assign  f31=txt[71:64];assign  f32=txt[39:32];assign  f33=txt[ 7: 0];

endmodule
